Power on reset (POR) circuits are well known in the art. These circuits operate in response to a rising supply voltage to control the logic state of a digital output signal to switch state values only after the rising supply voltage exceeds a threshold.
Reference is now made to FIG. 1 showing a circuit diagram for a conventional power on reset circuit 10. The circuit 10 receives power from a positive supply node 12 and a ground supply node 14. The circuit 10 includes a first circuit leg 16 comprising a series connection of a diode-connected p-channel MOSFET 18 and a resistive divider 20 formed by resistor R1 and resistor R2. The resistive divider 20 is connected between the drain terminal of transistor 18 and the ground supply node 14. The circuit 10 includes a second circuit leg 22 comprising a series connection of a p-channel MOSFET 24 and an n-channel MOSFET 26. The source terminals of transistors 18 and 24 are connected to the positive supply node 12. The gate terminals of transistors 18 and 24 are connected together. The transistors 18 and 24 accordingly form a current mirror circuit. The drain terminals of transistors 24 and 26 are connected together at node 28. A center tap node 30 of the resistive divider 20 is connected to the gate terminal of transistor 26. The source terminal of transistor 26 is connected to the ground supply node 14.
The circuit 10 further includes a Schmitt trigger circuit 34 having an input connected to node 28. The circuit also includes a logic NOT gate (inverter) 36 having an input connected to the output 38 of the Schmitt trigger circuit 34. The power on reset (POR) signal is generated at the output of the NOT gate 36.
The circuit 10 operates as follows: as the Vana voltage at the positive supply node 12 begins to rise, the transistors 18 and 24 are turned on. The voltage of the POR output signal is at ground. The voltage at node 28 rises with the rising Vana voltage and eventually crosses the high trigger threshold of the Schmitt trigger 34 causing the output of the Schmitt trigger to switch to the Vana voltage. The NOT gate 36 inverts the logic high output of the Schmitt trigger 34 and drives the POR output signal to ground. As the Vana voltage continues to rise, the current flowing through the diode connected transistor 18 also flows through the resistive divider 20. A divided voltage is developed by the resistive divider 20 at the tap node 30 and applied to the gate of transistor 26. With increasing Vana voltage, the divided voltage at the tap node 30 eventually exceeds the threshold voltage of the transistor 26 and transistor 26 begins to turn on. This causes the voltage at node 28 to fall. The voltage at node 28 eventually falls below the low trigger threshold of the Schmitt trigger 34. At this point, the output of the Schmitt trigger transitions to ground. The NOT gate 36 inverts the logic low output of the Schmitt trigger 34 and drives the POR output signal to the Vana voltage. Operational waveforms for the circuit 10 are shown in FIG. 2.
The circuit 10 has a known disadvantage in that its operational threshold relates to the thresholds of the n-channel and p-channel MOSFET devices used in the circuit. Thus, the operational threshold exhibits a corresponding wide spread with process corner and temperature. There is accordingly a need in the art for a POR circuit having a consistent Vana voltage at which the POR output signal is asserted.